How To Compare A Parameter To A Register Binary Value In Verilog
iii. Data types¶
3.i. Introduction¶
In the Chapter 2, we used the data-types i.eastward. 'wire' and 'reg' to define '1-flake' & '2-bit' input and output ports and signals. Also, some operators east.k. 'and (&)' and 'or (|)' etc. were discussed. In this chapter, some more data is provided on these topics.
three.2. Lexical rules¶
Verilog is example sensitive linguistic communication i.due east. upper and lower case letters accept different meanings. Besides, Verilog is costless formatting language (i.e. spaces tin be added freely), simply we use the python like approach to write the codes, as it is clear and readable. Lastly in Verilog, '//' is used for comments; also, multiline comments can written between /* and */.
three.3. Data types¶
Information types can be divided into two groups as follows,
- Cyberspace group: Internet group represents the physical connection between components e.grand. wire, wand and wor etc. In the tutorials, we volition apply only one net data type i.e. 'wire', which is sufficient to create all types of designs.
- Variable group: Variable group represents the storage of values in the blueprint. It is always used for the variables, whose values are assigned inside the 'always' block. Also, input port can not be defined every bit variable group. 'reg' and 'integer' are the example of variable group, which tin can be synthesized. We volition use merely 'reg' for designing purpose.
3.four. Logic values¶
Verilog has four logic values i.e. 0, ane, z and 10 as shown in Table 3.i,
| Logic | Clarification |
|---|---|
| 0 | logic '0' or false condition |
| 1 | logic '1' or truthful status |
| z | high impedance state (used for tri-state buffer) |
| 10 | don't care or unknown value |
3.5. Number representation¶
The number can be represented in various format as follows, which are listed in Table 3.two. Note that, 'reg' can be replaced with 'wire' in the tabular array.
- Binary Format
reg [ i : 0 ] a = 2 'b01 ; // number = 1; size = 2 scrap; reg [ 2 : 0 ] a = - 3 'b1 ; // unsigned number= -ane (in ii's complement form); size = three bit; - Decimal Format
reg [ three : 0 ] a = three 'd1 ; // number = i; size =3 bit; reg [ 3 : 0 ] a = - 3 'd1 ; // unsigned number = -i (in ii'southward complement form); size =3 chip; reg [ 3 : 0 ] a = 1 ; // unsigned number = 1; size = 4 bit; reg [ 3 : 0 ] a = - 1 ; // unsigned number = -1; size = 4 bit in 2's complement course; - Signed Decimal Form
integer a = one ; // signed number = i; size = 32 bit; integer a = - 1 ; // signed number = -1; size = 32 bit in 2'south complement form; - For hexadecimal and octal representations utilise 'h' and 'o' instead of 'b' in binary format.
| Number | Value | Comment |
|---|---|---|
| reg [1:0] a = 2'b01; | 01 | b is for binary |
| reg [1:0] a = ii'b0001_1111; | 00011111 | _ is ignored |
| reg [2:0] a = -3'b1; | 111 | -1 in two's complement with 3 bit (unsigned) |
| reg [3:0] a = 4'd1; | 0001 | d is for decimal |
| reg [3:0] a = -4'd1; | 1111 | -1 in ii'due south complement with 4 bit (unsigned) |
| reg [v:0] a = 6'o12; | 001_010 | o is for octal |
| reg [five:0] b = 6'h1f; | 0001_1111 | h is for hexadecimal |
| reg [three:0] a = one; | 0001 | unsigned format |
| reg [3:0] a = -1; | 1111 | -ane in 2's complement with 4 bit (unsigned) |
| reg signed [3:0] a = 1; | 0001 | signed format |
| reg signed [three:0] a = -ane; | 1111 | -1 in 2'southward complement with four fleck (signed) |
| integer a = 1; | 0000_0000_…_0001 | 32 bit i.e. 31-zeros and one-1 (signed) |
| integer a = -1; | 1111_1111_…_1111 | -1 in ii's complement with 32 bit i.east. all 1 (signed) |
| reg [4:0] a = v'bx | xxxxx | x is don't intendance |
| reg [four:0] a = v'bz | zzzzz | z is high impedance |
| reg [iv:0] a = 5'bx01 | xxx01 | z is high impedance |
Note
- 'wire' and 'reg' are in unsigned-format by default. These can be used for synthesis and simulation.
- 'integer' is in signed-format past default. This should be used for simulation.
3.half dozen. Signed numbers¶
By default, 'reg' and 'wire' information type are 'unsigned number, whereas 'integer' is signed number. Signed number can be divers for 'reg' and 'wire' by using 'signed' keywords i.east. 'reg signed' and 'wire signed' respectively as shown in Table 3.2.
Also, 'signed numbers' tin can exist converted into 'unsigned numbers' using '$unsigned()' keyword e.1000. if 'a = -iii (i.e. 101 in two'due south complement notation)', then '$unsigned(a)' will be '5 (i.east. value of 101)'. Similarly, 'unsigned numbers' can be converted into 'signed numbers' using 'signed()' keyword.
Warning
Although, numbers can be converted from one form to another, but it should be avoided as it may results in errors which are hard to find.
iii.seven. Operators¶
In this department, diverse synthesizable operators of Verilog are discussed, which are shown in Tabular array 3.iii.
| Type | Symbol | Description | Note |
|---|---|---|---|
| Arithmetic | + | add | |
| - | subtract | ||
| * | multiply | ||
| / | divide | may not synthesize | |
| % | modulus (remainder) | may non synthesize | |
| ** | power | may non synthesize | |
| Bitwise | ~ | non | |
| | | or | ||
| & | and | ||
| ^ | xor | ||
| ~& or &~ | nand | mix 2 operators | |
| Relational | > | greater than | |
| < | less than | ||
| >= | greater than or equal | ||
| <= | less than or equal | ||
| == | equal | ||
| != | not equal | ||
| Logical | ! | negation | |
| || | logical OR | ||
| && | logical AND | ||
| Shift operator | >> | right shift | |
| << | left shift | ||
| >>> | right shift with MSB shifted to right | ||
| <<< | same as << | ||
| Chain | { } | Concatenation | |
| { { } } | Replication | "eastward.1000. { ii{iii} } = {iii 3}" | |
| Conditional | ? : | conditional | eastward.g. (2>iii) ? ane : 0 |
| Sign-format | $unsigned() | signed to unsigned conversion | $unsigned(-3) |
| $signed() | unsigned to signed conversion | $signed(3) |
three.eight. Arithmetic operator¶
Three arithmetics operators i.e. +, -, and * tin can be synthesized in verilog.
3.8.1. Bitwise operators¶
Four bitwise operator are available in verilog i.e. '&' (and), '|' (or), ' ^ ' (xor) and '~' (not). Further, we tin can combine these operators to define new operators east.g. '~&' or '&~' can be used every bit 'nand' operations etc.
3.eight.2. Relational operators¶
We already come across the equality relational functioning i.e. '==' in section Department 2.ii.four. Further, v relational operators are defined in verilog i.e. '>', '>=', '<', '<=' and '!='(not equal to).
iii.8.3. Logical operators¶
We already see the 'and' relational operation i.due east. '&&' in section Department 2.2.4. Farther, 3 relational operators are defined in verilog i.e. '||' (or), '&&' and '!'(negation).
3.8.iv. Shift operators¶
Verilog provides iv types of shif operators i.e. >>, <<, >>>, <<<. Let 'a = 1011-0011', then nosotros will have following results with these operators,
- a >>three = 0001-0110 i.east. shift 3 bits to right and make full the MSB with zeros.
- a << 3 = 1001-yard i.due east. shift 3 bits to left and fill up the LSB with zeros.
- a >>>three = 1111-0110 i.east. shift 3 bits to right and make full the MSB with sign bit i.e. original MSB.
- a <<<3 = 1111-0110 i.east. same equally a<<3.
3.8.5. Concatenation and replication operators¶
Concatenation functioning '{ }' is used to combine smaller arrays to create a large array as shown below,
wire [ 1 : 0 ] a = 2 b '0 i ; wire [ ii : 0 ] b = 3 b '0 01 ; wire [ 3 : 0 ] c ; assign c = { a , b } // c = 01001 is created using a and b; Replication operator is used to repeat certain bits as shown below,
assign c = { 2 { a }, ane 'b0 } // c = 01010 i.e. a is repeated two times i.e. 01-01 3.eight.vi. Conditional operator¶
Conditional operator (?:) tin be defined as follows,
assign c = ( a > b ) ? a : b ; // i.e. c=a if a>b; else c=b; Also, conditional expression tin can exist cascaded as shown in Listing three.i, where 4x1 multiplexer is designed. Multiplexer is a combinational circuit which selects one of the many inputs with selection-lines and directly it to output. Fig. 3.one illustrates the truth tabular array for 4x1 multiplexer. Here 'i0 - i3' the input lines, whereas 's0' and 's1' are the selection line. Base of operations on the values of 's0' and 's1', the input is sent to output line, due east.g. if s0 and s1 are 0 then i0 will exist sent to the output of the multiplexer.
Fig. iii.1 Truth table of 4x1 multiplexer
Listing 3.1 Cascaded provisional operator¶
1 two 3 iv 5 6 7 8 9 ten 11 12 13 fourteen | // conditionalEx.5 module conditionalEx ( input wire [ 1 : 0 ] due south , input wire i0 , i1 , i2 , i3 , output wire y ); assign y = ( southward == 2 'b00 ) ? i0 : // y = i0 if south=00 ( due south == ii 'b01 ) ? i1 : // y = i1 if due south=01 ( due south == ii 'b10 ) ? i2 : // y = i2 if s=ten ( south == 2 'b11 ) ? i3 : // y = i3 if south=11 y ; // else y = y i.e. no modify endmodule |
The pattern generated in Fig. 3.2 is exactly same as the design generated past 'if-else argument' which is discussed in Department 4.7. Therefore, Fig. iii.2 is described and compared with other designs in Section iv.vii. Further, Fig. iii.3 shows the output waveform of the multiplexer which is generated by Listing 3.1.
Fig. iii.2 Multiplexer generated by List three.1
Fig. 3.iii Waveforms of Listing 3.one
3.8.vii. Parameter and localparam¶
Parameter and localparam are used to create reusable codes along with avoiding the 'hard literals' from the code every bit shown in following department.
3.8.eight. localparam¶
'localparam' keyword is used to defined the constants in verilog. In Listing 3.2, N is defined in line viii with value three. Then this value is used in line x and 11. Suppose we want to change the constant value to 4. Now, we need to change information technology only at one place i.eastward. line eight (instead of changing everywhere in the code e.chiliad. line ten and 11 in this example). In this way, we can remove the hard literals from the codes.
Listing 3.2 Localparam¶
1 two iii iv v 6 7 8 9 10 xi 12 xiii 14 15 xvi | // constantEx.five module constantEx ( input wire [ 3 : 0 ] a , b , output wire [ iii : 0 ] z ); localparam N = 3 , 1000 = two ; //localparam wire [ Due north: 0 ] x ; wire [ ii ** N: 0 ] y ; // employ x and y here assign z = a & b ; endmodule |
- It is better to define the size of the local-parameters otherwise 32-bit signed-format will be used for the local parameters, equally shown below
// 32-chip signed-format localparam N = 3 , M = ii ; // N & Grand are 5 bit and 3 chip unsigned numbers respectively localparam N = 5 'd3 , M = three 'd2 ; 3.8.ix. Parameter and defparam¶
'localparam' tin not be modified afterwards annunciation. But we can define the parameter in the module, which can be modified during component instantiation in structural modeling style as shown beneath.
Explanation Listing three.3
In line 5, ii parameters are defined i.e. 'N' and 'M'. So ports 'a' and 'b' are defined using parameter 'N'. The always block (lines 13-19) compares 'a' and 'b' and set the value of 'z' to one if these inputs are equal, otherwise ready 'z' to 0.
Listing 3.3 Parameter¶
Explanation Listing three.4 and List 3.5
In line v, 'a' and 'b' are divers as 4-scrap vector. Structural modeling is used in Line 9, where parameter mapping and port mapping is performed. Annotation that, in line xvi, '.N(v)' volition override the default value of N i.e. N=ii in Listing 3.iii. As well, parameter 'M' is not mapped, therefore default value of M volition be used, which is defined in Listing iii.3. In this way, we can remove 'hard literals' from the codes, which enhances the reusability of the designs. Value of the parameter 'N' can also be set using 'defparam' keyword, as shown in List 3.5.
Listing 3.four Parameter instantiation¶
Listing 3.5 Parameter instantiation using 'defparam'¶
- It is better to define the size of the parameters otherwise 32-bit signed-format will be used for the parameters, equally shown below
// 32-bit signed-format parameter North = 2 , M = 3 // N & One thousand are 5 bit and 4 fleck unsigned numbers respectively parameter Due north = 5 'd2 , 1000 = 4 'd3 ; 3.ix. Determination¶
In this chapter, we saw various data types and operators. Further Parameters and localparam are shown which tin be useful in creating the reusable designs.
Source: https://verilogguide.readthedocs.io/en/latest/verilog/datatype.html
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