Introduction to MDIO:

Management Data Input/Output (MDIO), or Media Independent Interface Management (MIIM) is a serial passenger vehicle protocol defined for the IEEE 802.3 standard Ethernet serial of Media Independent Interface (MII). MII connects media access control (MAC) devices to Ethernet physical layer (PHY) circuits. The SMI protocol is a simple two-wire serial interface that connects the direction unit to the managed PHY to command the PHY and capture the condition of the PHY. The Management Data Input/Output (MDIO) component tin can exist used to read and write the PHY control register. Each PHY can be monitored before operation and the connection status can be monitored during functioning. These registers provide status and control information such as: link status, speed ability and pick, power downwardly for depression power consumption, duplex mode (full or half), auto-negotiation, fault signalling, and loopback. The main purpose of using SMI protocol is to configure the PHY layer transceiver parameters, for example PHY devices can perform pre-emphasis or de-accent in the Physical Coding Sublayer (PCS), programming the command status registers in the PHY layer.

MDIO is a bidirectional shared autobus structure that tin can provide a connection from the MAC (master) up to 32 PHY (slave) devices. All data is synchronously transmitted with respect to the Management Data Clock (MDC), which is provided by the MAC and sent to all receiving devices. The data line is a tri-state shared bus that is MAC controlled for a write transaction or PHY controlled during a read transaction. The MDIO interface clock (MDC) supports frequency up to 2.5MHz. The host processor, which is responsible for arrangement configuration and monitoring, usually uses the MDIO host to perform individual access to various devices. MDIO was originally defined in Clause 22 of IEEE 802.3. To meet the growing needs of 10 Gigabit Ethernet devices, clause 45 of the 802.3ae specification is introduced.

MDIO System:

The MDIO double-decker has 2 signals: management data clock (MDC) and direction data input/output (MDIO). MDIO has specific terms to define various devices on the bus. The device driving the MDIO jitney is identified as a station management entity (STA). Target devices managed past MDC are chosen MDIO manageable devices (MMD). STA initiates all communications in MDIO and is responsible for decision-making the clock on MDC. The specified frequency of MDC is up to 2.5 MHz. Following Figure captures the interface wiring diagram of a typical MDIO system.

Figure one: Wiring diagram of a typical MDIO Awarding.

MDIO (SMI Protocol) Features:

  • SMI protocol has a configurable physical address.
  • MDC (clock bus) is specified to have a frequency up to 2.5 MHz.
  • Capability added to accost more registers–upwardly to 65,536 registers in each device.
  • Variable SMI speeds and duty bike.
  • Power down for low ability consumption.

SMI Protocol Frame Format:

CLAUSE 22:

Effigy ii: Clause 22 Frame format.

The MDIO data format for clause 22 is defined in the IEEE 802.3 Ethernet standard, as shown in the figure above.

Preamble (PRE): The kickoff field in the SMI protocol is indicated with Preamble. When the Preamble is sent, the MAC sends all bits as 1's in the MDIO line. The 32 bits in the preamble are always 1's.

Start (ST): The preamble is succeeded by the starting time bit which is two $.25 in size that remains 01 always in the clause 22 for both read or write operations.

Opcode (OP): The next field is the opcode which basically gives data whether read or write operation to be performed. Opcode with the value of '01' in the frame specifies the write operation. Similarly, Opcode with the value of '10' in the frame specifies read operation.

Physical Address (PHYAD): This field contains v-bit PHY address.

Register Address (REGAD): This field is 5 bit long indicating the annals to be written or read from.

Plough Effectually (TA): The Turnaround field is ii bits in size. When information is written to the PHY, the MAC will write "10" to the MDIO coach. When reading data, the MAC releases the MDIO bus.

Data: This field is a 16-flake broad. During the read educational activity, the PHY scrap writes the data read from the REGAD annals respective to the PHYAD in Data. During the write education, the MAC writes the value of the REGAD annals corresponding to the PHYAD in Data.

Idle: At this state, MDIO is driven to a high impedance state, simply it is generally pulled up with the help of pull-up resistor.

CLAUSE 45:

Since there is not enough registers for the future use, there was a need for Clause 45 to encounter the growing needs 10-fleck gigabit ethernet devices. There was little scope to cater multi devices PHY layer.

In addition to read and write in Clause 22, additional commands are added in the Clause 45. Clause 45 added back up for depression voltage devices down to 1.2V and extended the frame format to provide access to many more than devices and registers.

The MDIO data format for clause 45 is defined in the IEEE 802.3 Ethernet standard, equally shown in the effigy above.

Advantages of clause 45 over clause 22 are as follows:

  • Accessibility of 65,536 registers in 32 different devices across 32 dissimilar ports.
  • Boosted OP and ST code for indirect access to register accost for 10 Gigabit Ethernet.
  • Terminal mistake signaling.  Multiple repeaters.
  • Low voltage specification

Figure 3: Clause 45 Frame Format

Preamble (PRE): The first field in the SMI protocol is indicated with Preamble. When the Preamble is sent, the MAC sends all bits as one'southward in the MDIO line. The 32 bits in the preamble are always 1's.

Start (ST): The preamble is succeeded past the kickoff fleck which is 2 bits in size that remains 00 always in clause 45 for all operations.

Opcode (OP): The next field is the opcode which gives information on whether read or write operation to be executed. Opcode with the value of '01' in the frame specifies the write functioning. The opcode with the value of 11 specifies read performance. At that place exist boosted ii commands namely read increment and address. The read increment with opcode 10 basically does read operation with the MMD device address incrementing after each access. The opcode with value 00 is to rewrite or reread DEV Add's address register.

Physical Accost (PRTAD): This field consists of the v-bit PHY address.

Device Accost (REGAD): This field is five $.25 long indicating the registered address that must be written or read from.

Turn Around (TA): The Turnaround field is 2 bits in size. When data is written to the PHY, the MAC will write "ten" to the MDIO line. When reading data, the MAC releases the MDIO charabanc to initiate driving read information if read performance.

Information: This field is 16-bit broad. During the read teaching, the PHY fleck writes the information read from the REGAD register corresponding to the PHYAD in Data. During the write teaching, the MAC writes the value of the REGAD register corresponding to the PHYAD in Data.

Idle: At this country, the MDIO autobus is driven to a high impedance state, but it is pulled upward through a pull-up resistor of 1.5k ohm.

Theory of Operation:

The PHY devices crave a preamble of 32 1'due south that must exist sent by the MAC to PHY on the MDIO line. The annals admission consists of sixteen control $.25 followed past 16 information bits. The command bits consist of 2 offset bits, ii $.25 for opcode or the type of operation (read or write), the PHY address (5 $.25), the register address (five bits), and two turnaround bits. In a write instruction, the MAC provides the accost and data. For a read instruction, the PHY receives from the MDIO stream during the turnaround, supplies the MAC with the requested register data, and and so releases the MDIO stream.

When the MAC is driving the MDIO line, information technology must guarantee a steady value of 10 ns (setup fourth dimension) before the rising edge of the MDC clock. In add-on, the MDIO must remain stable 10 ns (hold time) after the rise border of the MDC. When the PHY drives the MDIO line, the PHY must provide an MDIO signal between 0 and 300 ns after the ascent edge of the clock.

Therefore, with a minimum clock interval of 400 ns (max clock rate is 2.5 MHz), the MAC can safely sample the MDIO during the second half of the depression clock wheel. The entire MDIO line is sampled on the rising edge of the clock except read functioning. During the read operation, the MDIO line is sampled on the falling border of the clock.

Figure four: Theory of operation for clause 22.

In one case the preamble is sent, the next two bits indicate the get-go performance. The start field is followed by read or write performance. The corresponding PHY address is and then sent on the MDIO line. The register accost of the PHY is then sent on the MDIO line. Both the addresses are 5 bits wide. During the turnaround, When the information is written to PHY, the MAC basically sends "10" indicating line is free for the data to be written.

During the read operation, The MAC releases the MDIO line. The data is sampled during the read functioning on the falling edge of the clock. If at that place is a mismatch with the PHY address, The value after the TA field will exist continuously high. This ways to say that MAC is trying to write to the annals that does not exists.

Since in that location is a limit of using the only a 5-flake addresses for both PHYADDR and REGADDR, it limits the number of MMD'southward the STA can communicate with. Besides, MDIO clause 22 only supports 5V tolerant devices and at that place is no depression voltage choice.

The main change in Clause 45 is how the registers are accessed. In Clause 22, both the accost and read or write data are specified in ane frame. Clause 45 changes this paradigm. Offset, an address frame indicating the MMD, and the register is sent. And so a second read or write frame is sent.

An reward of adding this two-wheel access is that clause 45 is backward uniform with clause 22, assuasive the devices to communicate with each other. Second, past creating an accost frame, the register address infinite is increased from 5 to 16 bits, which allows the STA to access 65,536 dissimilar registers. For this purpose, various changes accept been made to the composition of the data frame. A new opcode (00) is defined to identify the data frames according to clause 45.

The OP codes have been extended to define an accost frame, a write frame, a read frame or an incremental read and postal service-read accost frame. Since the register address is no longer needed, this field is replaced with DEVADDR to indicate the type of target device. The extended device type allows the STA to access other devices in add-on to the PHY.

SMI Protocol Challenges in Debug:

The SMI Protocol Analyzer (PGY-SMI-EX-PD) is a device that captures the data from the host and pattern under test. PGY-SMI-EX-PD is a leading tool that enables the design and test engineers to evaluate the respective SMI designs for its specifications by configuring the PGY-SMI-EX-PD as chief/secondary device, generating SMI traffic and decoding the SMI protocol decode packets.

Figure 5: SMI Protocol Analysis for clause 22 using PGY-SMI-EX-PD

PGY-SMI-EX-PD can generate a traffic by calculation a main or a slave device and and then helps in decoding the packets with fault injection adequacy. User can easily select the clause with the aid of Graphical User Interface (GUI). PGY-SMI-EX-PD provides an selection to generate the traffic through predefined scripts. The user tin can also configure the PHYADDR and REGADDR.

User can capture protocol action at specific event and decode the transition betwixt master and the slave. The decoded results tin exist viewed in timing diagram and Protocol listing window with autocorrelation. This comprehensive view of information makes it industry best, offer an easy-to- use solution to debug the SMI protocol action.

Figure 6: SMI Protocol Analysis for clause 45 using PGY-SMI-EX-PD

Timing view provides the plot of MDC and MDIO signals with bus diagram. Overlaying of Protocol bits on the digital timing waveform will help piece of cake debugging of Protocol decoded information. Cursor and Zoom features will make it user-friendly to clarify Protocol in timing diagram for any timing errors. Protocol window provides the decoded packet information in each country and all packet details with error info in packet. Selected frame in Protocol listing window will be auto correlated in timing view to view the timing data of the package.